期刊名称：International Journal of Electrical and Computer Engineering
电子版ISSN：2088-8708
出版年度：2013
卷号：3
期号：5
页码：577-583
DOI：10.11591/ijece.v3i5.3164
语种：English
出版社：Institute of Advanced Engineering and Science (IAES)
摘要：In this paper a low-power double-edge triggered static flip-flop (DETSFF) suitable for low-power and high performance applications is presented. The designed DETFF is verified at gpdk 180nm-1.8V CMOS technology. Comparison with some of the latest DETFFs shows that the proposed DETSFF can achieve the lowest power consumption, lowest clock to Q delay and thus Power-delay-product (PDP). Moreover, the proposed DETSFF comprises of only 15 transistors hence require lesser number of transistors and thus requires lesser overall silicon area.
关键词：VLSI Design;Dual Edge Triggered; Flip flop; High speed; Low Power; Static D Flip Flop
