摘要：3-input AND/XOR is the basic complex gate of Reed-Muller logic. Low energy consumption is important for Reed-Muller logic circuit implementation. Against the drawbacks of the published gate-level and transistor-level 3-input AND/XOR gate design in power and power delay product (PDP), a low energy consumption 3-input AND/XOR gate is proposed by employing multi-rails and hybrid-CMOS techniques to improve its speed and short the signal transimission path. Under 55nm CMOS process, post-simulations in different process corners are carried out by using HSPICE and compared with the published circuits. Simulation results show that the proposed circuit has advantages over published designs. For typical process corners, the improvement of the proposed circuit can be up to 27.21%, 19.23% and 35.39%, respectively, in terms of power, delay and power delay product.
