期刊名称：Advances in Computer Science and its Applications
印刷版ISSN：2166-2924
出版年度：2012
卷号：2
期号：1
页码：302-305
语种：English
出版社：World Science Publisher
摘要：In communication systems, n-bit parity problem (NPP) is widely used for error detection and correction. In this paper, an efficient architecture for hardware implementation of NPP is proposed. For this purpose, first we introduce extending single neuron that can be trained by perceptron learning rule to solve 2-bit and 3-bit parity problems. Then, we present novel architecture of cascaded modular neural networks, based on the presented neuron, with O(n/2) nodes and with O(2n) connections to solve NPP. The main advantages of proposed parity networks are low number of neurons, connecting weights and inputs for each neuron.
