摘要：The development a high-performance design of analog circuits becomes increasingly challenging with the continuous trend towards reducing the voltage supply and low power consumption without neglecting the trade-off among other performance parameters. This paper presents the design and implementation of CMOS operational amplifier (op-amp) with integrated common-mode feedback (CMFB) circuit for data converter using 0.13-μm Silterra CMOS technology. The folded cascode topology is employed as a main op-amp design because it provides high gain and high bandwidth besides low power consumption. The simulation results indicate that the DC gain of 64.5 dB along 133.1 MHz unity gain bandwidth (UGB) is achieved for a 1 pF load capacitor. The slew rate of 22.6 V/μs, the phase margin (PM) of 68.4° with settling time of 72.4 ns are obtained. The power consumption of this op-amp is 0.3 mW through voltage supply of 1.8 V.
