摘要：The most important mathematical operation is addition. Other operations such as subtraction, multiplication and division are usually implemented by adders. An efficient adder can be of great assistance in designing arithmetic circuits. QCA is a promising technology which seems to be a good candidate for the next generation of digital systems. So, an efficient QCA full-adder will facilitate creating QCA computational and arithmetic systems. In this paper, two high performances QCA full-adders are presented. They have a very dense structure and constructed using new kinds of five-input majority gates. One of the proposed designs has a robust structure. In this design the presented design rules for constructing a robust QCA circuit have been considered. In contrast to the previous designs constructed using a five-input majority gate, in the proposed QCA full-adders the outputs come out from the same side of the circuit. Also, the input and output signals are not surrounded by the other cells and can easily be accessed. The proposed robust QCA full-adder dominates all the previous robust designs in terms of area, delay and complexity. Using this design, ripple carry adders with different word sizes (that is, 4, 8 and 16) are constructed. In this paper, QCA designer, a common QCA layout design and verification tool is employed to verify and simulate the proposed five-input majority gates and QCA full-adders.
