期刊名称：International Journal of Computer Science & Information Technology (IJCSIT)
印刷版ISSN：0975-4660
电子版ISSN：0975-3826
出版年度：2013
卷号：5
期号：4
页码：53
出版社：Academy & Industry Research Collaboration Center (AIRCC)
摘要：A complex SoC typically consists of numerous of memories in today's digital systems. This paper presents atest/ repair flow based on memory grouping strategy and a revised distributed BIST structure for complexSoC devices. A gated selecting method is added to the distributed BIST structure. Also, this paper for thefirst time proposes a robust post repair stage based on BIRA and memory grouping in test flow. Simulationresults by mathematical method show that the proposed test flow has achieved a significant increase inyield of memories.
