期刊名称：International Journal of Computer Science & Information Technology (IJCSIT)
印刷版ISSN：0975-4660
电子版ISSN：0975-3826
出版年度：2014
卷号：6
期号：4
页码：75
出版社：Academy & Industry Research Collaboration Center (AIRCC)
摘要：As the complexity of the scan algorithm is dependent on the number of design registers, large SoC scandesigns can no longer be verified in RTL simulation unless partitioned into smaller sub-blocks. This paperproposes a methodology to decrease scan-chain verification time utilizing SCE-MI, a widely usedcommunication protocol for emulation, and an FPGA-based emulation platform. A high-level (SystemC)testbench and FPGA synthesizable hardware transactor models are developed for the scan-chain ISCAS89S400 benchmark circuit for high-speed communication between the host CPU workstation and the FPGAemulator. The emulation results are compared to other verification methodologies (RTL Simulation,Simulation Acceleration, and Transaction-based emulation), and found to be 82% faster than regular RTLsimulation. In addition, the emulation runs in the MHz speed range, allowing the incorporation of softwareapplications, drivers, and operating systems, as opposed to the Hz range in RTL simulation or submegahertzrange as accomplished in transaction-based emulation. In addition, the integration of scantesting and acceleration/emulation platforms allows more complex DFT methods to be developed andtested on a large scale system, decreasing the time to market for products.
