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  • 标题:Estimation of Optimized Energy and Latency Constraint for Task Allocation in 3d Network on Chip
  • 本地全文:下载
  • 作者:Vaibhav Jha ; Mohit Jha ; G K Sharma
  • 期刊名称:International Journal of Computer Science & Information Technology (IJCSIT)
  • 印刷版ISSN:0975-4660
  • 电子版ISSN:0975-3826
  • 出版年度:2014
  • 卷号:6
  • 期号:2
  • 页码:67
  • 出版社:Academy & Industry Research Collaboration Center (AIRCC)
  • 摘要:In Network on Chip (NoC) rooted system, energy consumption is affected by task scheduling and allocationschemes which affect the performance of the system. In this paper we test the pre-existing proposedalgorithms and introduced a new energy skilled algorithm for 3D NoC architecture. An efficient dynamicand cluster approaches are proposed along with the optimization using bio-inspired algorithm. Theproposed algorithm has been implemented and evaluated on randomly generated benchmark and real lifeapplication such as MMS, Telecom and VOPD. The algorithm has also been tested with the E3S benchmarkand has been compared with the existing mapping algorithm spiral and crinkle and has shown betterreduction in the communication energy consumption and shows improvement in the performance of thesystem. On performing experimental analysis of proposed algorithm results shows that average reductionin energy consumption is 49%, reduction in communication cost is 48% and average latency is 34%.Cluster based approach is mapped onto NoC using Dynamic Diagonal Mapping (DDMap), Crinkle andSpiral algorithms and found DDmap provides improved result. On analysis and comparison of mapping ofcluster using DDmap approach the average energy reduction is 14% and 9% with crinkle and spiral.
  • 关键词:Network on Chip; Mapping; 3D Architecture; System on Chip; Optimization
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