摘要：The design complexity of systems on a chip drives the need to reuse legacy or intellectual property cores, whose gate-level implementation details are unavailable. The core test depends on manufacturing technologies and changes permanently during a design lifecycle. In this paper we consider the impact of circuit realization on the fault coverage of the test set. We have performed various comprehensive experiments with combinational benchmark circuits. Our experiments show that the test sets generated for a particular circuit realization fail to detect in average only less than one and a half percent of the stuck-at faults of the re-synthesized circuit but in some cases this figure is more than nine percent. The double test sets declined almost twice both the maximum and the average percent of undetected faults. The experiments exhibit that the supplement of the test set with sensitive adjacent test patterns significantly increases the fault coverage of the re-synthesized core.
