摘要：AbstractA method is proposed for implementing Mealy FSMs logic circuits with embedded memory blocks. The method is based on encoding of the rows of FSM structure table and replacement of logical conditions. Example of design and results of investigations are given. Our approach allows diminishing the number of LUTs in the block of RLC due to splitting the initial set of logical conditions. Also it results in the decrease of used EMBs for around 15% of standard benchmarks.
