摘要：AbstractThe paper presents a new approach to improve efficiency of the verification process through acceleration of tests. The verification eco-system based on well-accepted industry standards, consisting of essential functionality and an emulation platform is described in the article. The JPEG2000 encoder has been developed with the use of this emulation platform in order to verify both, the new approach and the possibility of reducing verification process time. The new approach allows to save verification time, due to significant reduction of tests execution time. Additionally, a debug capability, which is provided by the emulation system, enables quick identification and elimination of implementation bugs. The presented solution can be supported by Universal Verification Methodology (UVM) like methodology to create the best suited environment. In order to use such methodology, the SystemC language has been enhanced by UVM-SystemC library. The library in combination with the approach presented in the paper and the use of the emulation platform can deliver the complete system to verify IP cores of average complexity. It gives an opportunity to avoid a commercial logic simulator within the verification process.
