摘要：AbstractAs one of the crucial semiconductor manufacturing steps, chip packaging process plays an important role to provide a phys ical protection, electric interconnection environment for naked wafer. In the present work, the chip packaging process is analyzed in detail for process understanding and monitoring. First, detailed description of the chip packaging process is given to help better understand the process. Then, the underlying process characteristics are explored and multi-stage nature of chip packaging process is revealed by t racking changes of process variable correlat ions. The whole process is divided into several modeling phases using a step-wise sequential phase partition algorithm, agreeing well with the real process. Stage-based online monitoring and fault diagnosis is performed to analyze some common abnormal behaviors in this process. The stage-based analysis results not only provide reliable online monitoring and fault diagnosis performance but also provide enhanced process understanding.
