摘要：AbstractWe propose a new logic ofvalued Booleansfor writing properties which are not just true or false but compute how severely they are falsified. The logic is reminiscent of STL or MTL but gives the tester control over what severity means in the particular problem domain. We use this logic to simplify failing test inputs in the context of random testing of cyber-physical systems and show that it improves the quality of counterexamples found. The logic of valued Booleans might also be used as an alternative to the standard robust semantics of STL formulas in optimization-based approaches to falsification.
关键词：KeywordsReachability analysisverificationabstraction of hybrid systemsembedded computer control systemsapplicationslogical designphysical designimplementation of embedded computer systemssupervisiontestingmodel-driven systems engineering
