期刊名称：International Journal of Computer Science & Technology
印刷版ISSN：2229-4333
电子版ISSN：0976-8491
出版年度：2012
卷号：3
期号：4
页码：301-304
语种：English
出版社：Ayushmaan Technologies
摘要：This paper describes an error-correcting code (ECC) block for use with the DDR and DDR2 SDRAM controller Cores. The ECC block comprises an encoder and a decoder cum corrector, which can detect and correct single-bit errors and detect double-bit errors. It is a cost-efficient solution that is fast, has a low latency, no detrimental effect on system performance, and uses minimal system resources. The ECC block uses an 8-bit ECC for each 64-bit message. Fully parameterized Hamming code ECC block with 8-bit ECC for 64-bit message Configurable latency of 1 or 2 clock delay during writes and 2 or 3 clock delay during reads. Detect any single- and double bit error on the first clock and correct any detected single-bit errors on the second clock. Index Terms—Error Correction, Hamming code, SEC-DED, Parity, Encoding, Syndrome, Mask, Decoding.
