期刊名称：International Journal of Computer Science & Technology
印刷版ISSN：2229-4333
电子版ISSN：0976-8491
出版年度：2012
卷号：3
期号：4
页码：293-297
语种：English
出版社：Ayushmaan Technologies
摘要：Message authentication is an important technique in information security to verify that whether the communicating entity is the one that it claims to be and have not been altered. Cryptographic hash functions are very important for securing the information against the unspecified attacks. They are used to compress and encrypt large messages in to a smaller message digest. SHA-1 (Secure Hash Algorithm – 1) is one implementation of such hash functions that takes in messages of size less than 264 bits and produces a 160 bit message digest. Secure Hash Algorithm 1 (SHA-1) has been used in Internet Protocol Security (IPSEC). This paper addresses the design, simulation and characterization of a reusable soft IP Core for SHA-1 computer.The proposed design was modeled using Verilog HDL and also prototype on ALTERA® platform FPGA.
