期刊名称：International Journal of Computer Science & Technology
印刷版ISSN：2229-4333
电子版ISSN：0976-8491
出版年度：2013
卷号：4
期号：3
页码：282-285
语种：English
出版社：Ayushmaan Technologies
摘要：High-speed routers rely on well-designed packet buffers that support multiple queues, provide large capacity and short response times. Some researchers suggested combined SRAM/ DRAM hierarchical buffer architectures to meet these challenges. However, these architectures suffer from either large SRAM requirement or high time-complexity in the memory management. In this paper, we present scalable, efficient, and novel Data Dissemination architecture. Two fundamental issues need to be addressed to make this architecture feasible: (1) how to minimize the overhead of an individual packet buffer; and (2) how to design scalable packet buffers using independent buffer subsystems. We address these issues by first designing an efficient compact buffer that reduces the SRAM size requirement by (k – 1 )/k. Then, we introduce a feasible way of coordinating multiple subsystems with a load-balancing algorithm that maximizes the overall system performance. Both theoretical analysis and experimental results demonstrate that our load-balancing algorithm and the Data Dissemination architecture can easily scale to meet the buffering needs of high bandwidth links and satisfy the requirements of.
