期刊名称：International Journal of Computer Science & Technology
印刷版ISSN：2229-4333
电子版ISSN：0976-8491
出版年度：2013
卷号：4
期号：4
页码：104-108
语种：English
出版社：Ayushmaan Technologies
摘要：Trusting on the well-designed packet buffers in the high-speed routers in the support of the multiple queues that provide large capacity and the short response time. In some researches, it is required to suggest the SRAM/DRAM hierarchical buffer architectures. The architectures suffer from either large SRAM requirement or high time-complexity in the memory management. In our research, we introduce the efficient, novel, and scalable distributed packet buffer architecture. To make the architecture feasible we have two fundamental issues that need to be addressed: a) How to minimize the overhead of an individual packet buffer b) how to design scalable packet buffers using independent buffer subsystems. We direct these problems by initial coming up with an efficient compact buffer that reduces the SRAM size demand by (k-1)/k. After, we present a feasible way of coordinating multiple subsystems with a load-balancing algorithm that maximizes the overall system performance. Our load-balancing algorithm and the distributed packet buffer architecture can easily scale to meet the buffering needs of high bandwidth links and satisfy the requirements of scale and support for multiple queues.
