期刊名称：International Journal of Computer Science & Technology
印刷版ISSN：2229-4333
电子版ISSN：0976-8491
出版年度：2014
卷号：5
期号：3
页码：31-34
语种：English
出版社：Ayushmaan Technologies
摘要：The demand for strong secure data transmission is increasing due to the tremendous development in digital telecommunication. One of the solutions for data security is cryptography. Hash functions are interesting and growing area in cryptography. The Secure Hash Algorithms (SHA) is the most popular cryptographic hash function. SHA 2 is a powerful hash function and it consist of four variants viz; SHA 224, SHA 256, SHA 384 and SHA 512.In this paper design, implementation and characterization of SHA 384 core is presented. Verilog HDL is used to model the hardware. Xilinx® Virtex®-6 FPGA (XC6VLX240T-1FF1156) is used to prototype the design. A throughput of 1673.6384Mbps is obtained.
