期刊名称：International Journal of Computer Science & Technology
印刷版ISSN：2229-4333
电子版ISSN：0976-8491
出版年度：2014
卷号：5
期号：3
页码：38-41
语种：English
出版社：Ayushmaan Technologies
摘要：The amount of sensitive data being transmitted over the internet has been increased due to the rapid development in communication industry. In this context, ensuring security has prime importance.Cryptography can address many security issues. Hash function is an interesting and growing area in cryptography. Secure Hash Algorithms (SHA) is a family of cryptographic hash functions.SHA 2 is a unifying name for the four hashing algorithms SHA 224, SHA 256, SHA 384 and SHA 512. In this paper design, implementation and characterization of SHA 512 core is presented.Verilog HDL is used to model the hardware. Xilinx® Virtex® -6FPGA (XC6VLX240T-1FF1156) is used to prototype the design.A throughput of 1623.3344Mbps is obtained.
