期刊名称：International Journal of Computer Science & Technology
印刷版ISSN：2229-4333
电子版ISSN：0976-8491
出版年度：2014
卷号：5
期号：3
页码：18-21
语种：English
出版社：Ayushmaan Technologies
摘要：To provide secure digital telecommunication cryptography is used. Hash function is an interesting and growing area in cryptography. Secure Hash Algorithms (SHA) is a family of cryptographic hash functions. SHA 2 consist of four variants viz; SHA 224, SHA 256, SHA 384 and SHA 512. In this paper design, implementation and characterization of SHA 224 core is presented. VerilogHDL is used to model the hardware. Xilinx® Virtex®-6 FPGA (XC6VLX240T-1FF1156) is used to prototype the design. A throughput of 1206.088Mbps is obtained.
