期刊名称：International Journal of Computer Science & Technology
印刷版ISSN：2229-4333
电子版ISSN：0976-8491
出版年度：2012
卷号：3
期号：1
页码：604-606
语种：English
出版社：Ayushmaan Technologies
摘要：An Arithmetic Logic Unit (ALU) is an integral part of a computerprocessor. It has the capability of performing a number of differentarithmetic and logic operations such as addition, subtraction, bitshifts and magnitude comparison. ALUs of various bit-widthsare frequently required in Very Large-Scale Integrated circuits(VLSI) from processors to Application Specifc Integrated Circuits(ASICs). In this paper, we present the design of a high performance4-bit ALU using CMOSandBiCMOS technologies for high speedapplications. Thease were further compared w.r.t. speed, powerdissipation and power delay product. The comparison of CMOSto BiCMOS often seen in the literature shows the delay of singlestage circuits driving a capacitive load, with the BiCMOS circuitexhibiting a bold advantage. TANNER EDA tools were used forschematic simulation. The simulation technology used was MOSIS200nm. This ALU can be used in mixed signal processing likeradar system, image recognition, high speed broadband networksetc. The analog input signal must frst be sampled and digitizedusing an ADC (analog to digital converter). The resulting binarynumbers, representing successive sampled values of the inputsignal, were transferred to the processor. The ALU of the processorcarried out numerical calculations with them. These calculationstypically involve multiplying the input values by constants andadding the products together.
