期刊名称：International Journal of Computer Science & Technology
印刷版ISSN：2229-4333
电子版ISSN：0976-8491
出版年度：2012
卷号：3
期号：2
页码：455-463
语种：English
出版社：Ayushmaan Technologies
摘要：Multiplication is one of the basic arithmetic operations and fundamental building block in all DSP task. The objective of good multiplier is to provide a physically compact, good speed and low power consumption. To save significant power consumption in VLSI design, it is good to reduce its dynamic power that is major part of total power dissipation. For higher order multiplications, a huge number of adders are to be used to perform the partial product addition. Reduction of adders by introducing special kind of adders that are capable to add five/six/seven bits per decade. These adders are called compressors. These compressors make the multipliers faster as compared to the conventional design. In this paper we present a comparative study of Array Multiplier, Wallace Tree Multiplier, Booth Multiplier for Area, Power, Speed in VLSI design of 8 bit Multipliers.
