出版社：Electronics and Telecommunications Research Institute
摘要：The increasing size and complexity of deep neural networks (DNNs) necessitate the development of efficient high‐performance accelerators. An efficient memory structure and operating scheme provide an intuitive solution for high‐performance accelerators along with dataflow control. Furthermore, the processing of various neural networks (NNs) requires a flexible memory architecture, programmable control scheme, and automated optimizations. We first propose an efficient architecture with flexibility while operating at a high frequency despite the large memory and PE‐array sizes. We then improve the efficiency and usability of our architecture by automating the optimization algorithm. The experimental results show that the architecture increases the data reuse; a diagonal write path improves the performance by 1.44× on average across a wide range of NNs. The automated optimizations significantly enhance the performance from 3.8× to 14.79× and further provide usability. Therefore, automating the optimization as well as designing an efficient architecture is critical to realizing high‐performance DNN accelerators.
