摘要：his paper deals with a logarithmic and a linear chirp sine generation on a fixed-pointFPGA mainly for vibration testing, nevertheless, the generator can also be used in other areas. A basicoverview of the logarithmic chirp sine signal is provided. Then, methods of software signal generationas well as different hardware platforms are briefly described and their pros and cons are mentioned. ADDS generator on FPGA needs the phase difference between samples as an input. This generation forthe logarithm chirp sine signal is presented, and its resolution, errors and limitations on fixed-pointarithmetic are revealed. Our implementation runs on Compact RIO 9067, uses 32-bit fixed-point and isable to generate linear and logarithm chirp signals from 10 Hz to 7 kHz with a minimum chirp speed of1 oct/min.
