期刊名称：Facta universitatis - series: Electronics and Energetics
印刷版ISSN：0353-3670
电子版ISSN：2217-5997
出版年度：2021
卷号：34
期号：2
页码：259-280
DOI：10.2298/FUEE2102259K
语种：English
出版社：University of Niš
摘要：Reduction in leakage current has become a significant concern in nanotechnology-based low-power, low-voltage, and high-performance VLSI applications. This research article discusses a new low-power circuit design the approach of FORTRAN (FORced stack sleep TRANsistor), which decreases the leakage power efficiency in the CMOS-based circuit outline in VLSI domain. FORTRAN approach reduces leakage current in both active as well as standby modes of operation. Furthermore, it is not time intensive when the circuit goes from active mode to standby mode and vice-versa. To validate the proposed design approach, experiments are conducted in the Tanner EDA tool of mentor graphics bundle on projected circuit designs for the full adder, a chain of 4-inverters, and 4- bit multiplier designs utilizing 180nm, 130nm, and 90nm TSMC technology node. The outcomes obtained show the result of a 95-98% vital reduction in leakage power as well as a 15-20% reduction in dynamic power with a minor increase in delay. The result outcomes are compared for accuracy with the notable design approaches that are accessible for both active and standby modes of operation.
关键词：FORTRAN approach; Submicron region; Standby and Active modes of operation; Power optimization; Sub-threshold leakage current
