期刊名称：Eastern-European Journal of Enterprise Technologies
印刷版ISSN：1729-3774
电子版ISSN：1729-4061
出版年度：2016
卷号：3
期号：4
页码：56-63
DOI：10.15587/1729-4061.2016.70355
语种：English
出版社：PC Technology Center
摘要：The operation of addition of binary numbers in the multi-bit parallel carry adder circuit of the Rademacher NTB, the process of which uses the logarithmic summation algorithm is considered. It is found that computing of the sum and carry signals in circuits of such adders can be justified by the mathematical model in the form of the directed acyclic graph, which is a binary tree. It is revealed that the performance indicator of the directed acyclic graph in the form of a number of computing steps determines the optimum number of carries in the multi-bit parallel carry adder circuit in the Rademacher NTB.It is found that the number of computing steps for the considered models of parallel carry adders is equal to the number of bits of binary numbers n. Thus, the complexity of the algorithm for computing the sum and carry signals of the parallel carry adder in the Rademacher NTB is O (n) and is linear – the time of the algorithm increases linearly with the number of bits of binary numbers n.The research can be used for the design technology of electronic adder circuits, since it makes clear what is the structure of the adder, teach to operate the adder circuit at the design stage.
