期刊名称：American Journal of Electrical and Electronic Engineering
印刷版ISSN：2328-7365
电子版ISSN：2328-7357
出版年度：2013
卷号：1
期号：2
页码：19-22
DOI：10.12691/ajeee-1-2-1
语种：English
出版社：Science and Education Publishing
摘要：In this paper, we propose a noise reduction method for a Vernier Time-to-Digital Converter (VTDC) using a first-order noise shaping structure and a gated ring oscillator (GRO). An 11bit VTDC with 4 p s effective resolution was designed and developed for a high performance All Digital Frequency Synthesizer (ADFS). The VTDC realized in 180nm CMOS, its power consumption depending on the time difference between input edges; 1 to 11mA from a 1.5 V supply.
关键词：vernier time-to-digital-converter; noise shaping; ring oscillator
