期刊名称：International Transaction of Electrical and Computer Engineers System
印刷版ISSN：2373-1273
电子版ISSN：2373-1281
出版年度：2014
卷号：2
期号：4
页码：114-119
DOI：10.12691/iteces-2-4-1
语种：English
出版社：Science and Education Publishing
摘要：Differential Power Analysis (DPA) presents a major challenge to mathematically secure cryptographic protocols. Attacks can break the encryption by measuring the energy consumed in the working digital circuit. To prevent this types of attack, this paper proposes the use of reversible logic for designing a high speed complex multiplier (ASIC) based on Vedic mathematics in cryptosystem. Reversible logic is gaining significance in the context of emerging technology such as quantum computing. Ideally, reversible circuits do not loose information during computation. Thus, it would be of great significance to apply reversible logic to design for secure cryptosystem. The idea for designing the multiplier unit is adopted from ancient Indian mathematics “Vedas”. On account of these formulas, the partial products and sums are generated in one step which reduces the carry propagation from LSB to MSB. The implementation of the vedic mathematics & their application to the complex multiplier ensure substantial reduction of propagation delay in comparison with DA based architecture (distributed arithmetic) & parallel adder based implementation which are commonly used. The functionality of these circuits was checked & performance parameters like propagation delay and dynamic power consumption were calculated by spice specter using standard 90nm cmos technology.
