摘要：Electronic circuits are composed of many complex arithmetic units. Multipliers are one of the basic arithmetic elements. Multipliers are essential component in most of the Digital Signal Processing applications, Image processing architectures and microprocessors. Area and speed are two major concerns for designing multipliers. Three operations are inherent in multiplication: partial products generation, partial products reduction and addition. A fast adder architecture therefore greatly enhances the speed of the overall process.Quaternary logic adder architecture is proposed that works on a hybrid of binary and quaternary number systems. A given binary string is first divided into quaternary digits of 2 bits each followed by parallel addition reducing the carry propagation delay. The design doesn’t require a radix conversion module as the sum is directly generated in binary using the novel concept of an adjusting bit.The proposed hybrid multiplier design is compared with an Existing multiplier based on multi voltage or multi value logic [MVL], Wallace Multiplier that incorporates a QSD adder with a conversion module for quaternary to binary conversion, Wallace multiplier that uses Carry Select Adder and a commonly used fast multiplication mechanism such as Booth multiplier. All these designs have been developed using Verilog HDL and synthesized by HDL Design Compiler..
