期刊名称：International Journal of Advances in Engineering and Management
电子版ISSN：2395-5252
出版年度：2020
卷号：2
期号：2
页码：5-10
语种：English
出版社：IJAEM JOURNAL
摘要：FPGA based Arithmetic Logic Unit has critical role in all processors; it is an inbuilt part of Central processing unit. Arithmetic Logic Unit is used to calculate the outputs of a large form of basic logical and arithmetic computations. In this paper, design and implementation of an optimized 64 bit ALU is proposed whose size can be reduced effortlessly to the 16 bit or 32 bit ALU. The proposed design is implemented using two level optimization, initially the resource utilization of FPGA is decreased with the help of recycling and reusing them for variety of operations. As a result of reduced FPGA utilization, FPGA resources will be saved as well as power consumption is also reduced. Different types of blocks are designed in order to carry out 16 operations. In final stage of optimization only single block is active at an instance and remaining blocks are inactive, which decreases the dynamic power utilization of the device and the design obtained is much energy efficient.
