期刊名称：International Journal of Communication and Computer Technologies
印刷版ISSN：2278-9723
出版年度：2017
卷号：5
期号：1
页码：1-5
DOI：10.31838/ijccts/05.01.01
语种：English
出版社：IJCCTS
摘要：A Full adder circuit is a very important component of the design of integrated circuits in VLSI design. In this paper represents a full adder using transmission gates at supply voltage is 1.8 dc voltages. The result of the post layout simulation (using CADENCE EDA TOOL) have been compare with the results of similar previously reported for adder circuits. In this proposed transmission gate circuits is very high efficient in terms of power, delay and area consumption compare too many other full adder circuits.
