期刊名称：International Journal of Electronics, Communication and Soft Computing Science and Engineering
印刷版ISSN：2277-9477
出版年度：2018
卷号：11
语种：English
出版社：IJECSCSE
摘要：In this paper, a scalable design of 2:4 Decoder has been designed to minimize power dissipation using 250nm, 180nm and 90nm CMOS technology. The proposed design has been simulated and analyzed in TANNER-13 EDA tool to make comparative study of power consumption at different technologies. The proposed scalable 2:4 Decoder using 90nm CMOS technology gives better results in terms of power consumption in 180nm and 250nm CMOS technologies. In this paper, also comparison of 2:4 decoders is done on the basis of average power consumption and maximum power consumption at constant voltages and at different nano-technologies.
