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  • 标题:REALIZATION OF SPEED OPTIMIZED VLSI ARCHITECTURE OF MULTISTAGE LINEAR FEEDBACK SHIFT REGISTER COUNTERS DECODING LOGIC
  • 本地全文:下载
  • 作者:SREEPADI PAVAN KUMAR ; Y. DAVID SOLOMON RAJU
  • 期刊名称:International Journal of Early Childhood Special Education
  • 电子版ISSN:1308-5581
  • 出版年度:2022
  • 卷号:14
  • 期号:2
  • 页码:1305-1313
  • DOI:10.9756/INT-JECSE/V14I2.116
  • 语种:English
  • 出版社:International Journal of Early Childhood Special Education
  • 摘要:When compared to standard binary counters, it has been discovered that linear-feedback shift register counters are ideally suited to applications needing huge arrays of counters that can improve both area of the design and performance.However, decoding the count order into binary necessitates a lot of processing, making system-on-chip designs impossible.A counter made up of many LFSR stagesis presented in this study using carry look ahead adder for high frequency applications that keep the advantages of a one-stage LFSR while only requiring decoding Circuitry that scales logarithmically with the number of stages instead of exponentially with the number of bits like other circuitry does.
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