出版社：The Institute of Image Information and Television Engineers
摘要：With the rapid development of the integrated circuit technology, the dynamic reconfigurable circuit has attracted much attention. The single circuit neuron MOS comparator has already been achieved. We propose the expansion of the circuit to achieve a multi-bit comparator. The proposed neuron MOS comparator is constructed by using only a two-stage neuron MOS inverter and an ordinary CMOS inverter. The newly designed circuit with an expanded Floating-Gate Potential Diagram (FPD) is described. The proposed circuit with three comparator functions is achieved using the single circuit. Applying this single circuit design technique, a multiple bits comparator can be achieved in a smaller area compared with that designed using the conventional circuit. The prototype of the newly proposed circuit was fabricated in the 1.2μm double poly-silicon CMOS process. The prototype device operates as well as the simulated one.
