摘要：Advanced video coding standards have become widely deployed in numerous products, such as multimedia service, broadcasting, mobile television, video conferences, surveillance systems and so on. New compression techniques are gradually included in video coding standards so that a 50% compression rate reduction is achievable every ten years. However, dramatically increased computational complexity is one of the many problems brought by the trend. With recent advancement of VLSI (the Very Large Scale Integration) semiconductor technology contributing to the emerging digital multimedia word, this paper intends to investigate efficient parallel architecture for the emerging high efficiency video coding (HEVC) standard to speed up the intra coding process, without any prediction modes ignored. Parallelism is achieved by limiting the reference pixels of the 4 × 4 subblocks, allowing the subblocks to use different direction modes to predict the residuals. Experimental implementations of the proposed algorithm are demonstrated by using a set of video test sequences that are widely used and freely available. The results show that the proposed algorithm can achieve a satisfying intra parallelism without any significant performance lose.
