摘要：This paper proposes a kind of project which is about FPGA (the Field Programmable Gate Array, FPGA) hardware implementation scheme for PID AQM algorithm. According to the analyses of the relatively mature discrete PID algorithm, we realized PID algorithm by using the combination of LPM (Library of Parameter Modules) macro module and Verilog code in FPGA. In this article, we write the program of serial communication to achieve data communication of FPGA with the router (Ipcop), and we use the interface to connect PID algorithm and FPGA serial communication module, the purpose of which is to achieve the control of PID algorithm to control network communication data flow. This article uses FPGA to reduce the consumption of router by achieving PID AQM algorithm, which can improve the algorithm’s speed of execution and the real time performance
