摘要：To aid in the hardware/software partitioning of the reconfigurable computing systems, it is necessary to conduct fast and accurate FPGA-based delay estimations before the partitioning. Most previous works predict the delay by adopting a high-level delay estimation based on empirical formulae. In such method, the empirical formulae are often obtained by a regression analysis on the real values reported by the synthesis and place-and-route tools of FPGAs. With alternative properties of tools or different FPGA devices, the empirical formulae need to be re-analyzed and decided. However, it is time-consuming due to inevitably repeated running synthesis and place-and-route tasks, which results in slow estimation and always beyond the tolerance of the estimation time. To address this problem, we present an improved high-level delay-estimation method in this article. We derived theory formulae called increasing formulae for HLL (High Level Language) operations from the basic idea of the hardware circuit design. These increasing formulae can be fit for most FPGAs. Combining the proposed formulae, the paper proposes a rapid estimation algorithm also. And the algorithm can obtain hardware delay of different hardware versions, thus reduces the number of times of running the time-consuming tasks greatly. Experimental results show that our method can achieve error within 2.69% for virtex-5 FPGA, compared with the real values.
