期刊名称：International Journal of Computer Trends and Technology
电子版ISSN：2231-2803
出版年度：2011
卷号：2
期号：2-2
出版社：Seventh Sense Research Group
摘要：This paper presents a new hardware efficient distributed arithmetic (DA) architecture for high order (> 1024) digital ?lter. The new architecture is termed reusable distributed arithmetic (RDA). The proposed architecture has a linear dependence of memory size on ?lters length versus the exponential Dependence found in lookup table (LUT)based designs by removing the LUT and generating the required combinations online. In addition, the proposed RDA architecture reuses the computation blocks much like the way multipliers are reused in multiplierbased architectures to reduce hardware complexity. The proposed RDA design is compared against a multiplierbased (MM) design to illustrate the area dependency of both designs on ?lters length. FPGA synthesis results con?rm that the RDA design is capable of much higher order ?lters (2048 tap) than the MM design (512 tap) while at the same time having similar equivalent gate counts and throughput.
关键词：Pattern Discovery in Mixed Data using Large Database
