期刊名称：International Journal of Computer Trends and Technology
电子版ISSN：2231-2803
出版年度：2014
卷号：7
期号：4
DOI：10.14445/22312803/IJCTT-V7P153
出版社：Seventh Sense Research Group
摘要：In the designing of any VLSI System, arithmetic circuits play a vital role, subtractor circuit is one among them. In this paper a Power efficient HalfSubtractor has been designed using the PTL technique. Subtractor circuit using this technique consumes less power in comparison to the CMOS and TG techniques. The proposed HalfSubtractor circuit using the PTL technique consists of 6 NMOS and 4 PMOS. The proposed PTL HalfSubtractor is designed and simulated using DSCH 3.1 and Microwind 3.1 on 120nm. The power estimation and simulation of layout has been done for the proposed PTL halfSubtractor design. Power comparison on BSIM4 and LEVEL3 has been performed with respect to the supply voltage on 120nm. Results show that area consumed by the proposed PTL HalfSubtractor is 147.8µm2 on 120nm technology. At 1V power supply the proposed PTL HalfSubtractor consumes 3.353µW power on BSIM4 and 3.546µW power on LEVEL3. The proposed circuit has also been compared with other Subtractor designs using CMOS and TG logics, and the proposed design has been proven power efficient as compared to design by other logics.
