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  • 标题:Efficient Layout Design of 4-Bit Full Adder using Transmission Gate
  • 本地全文:下载
  • 作者:Anurag Yadav ; Rajesh Mehra
  • 期刊名称:International Journal of Computer Trends and Technology
  • 电子版ISSN:2231-2803
  • 出版年度:2015
  • 卷号:23
  • 期号:3
  • 页码:116-119
  • DOI:10.14445/22312803/IJCTT-V23P125
  • 出版社:Seventh Sense Research Group
  • 摘要:In any digital circuit surface area and power both are very important parameters. In this paper 4 bit full adder using transmission gate is designed. To design 4 bit full adder two methods are used. First is semi custom design method and second is full custom design method. In first semi custom design method a layout of 4bit full adder is designed with available width and length of the transistor. In full custom design method create a layout with the help of reduced width of transistor. 4bit full adder has one important element which is full adder. Full adder is designed based upon transmission gate. Transmission gate is used to improve the logic level of signal. 90nm technology is used to simulate these two design methods. It can be found from the simulated results that full custom design layout results in 29.65% reduction of surface area of 4bit full adder as compared to semi custom design. It can also be observed from the simulated results that full custom layout results in 26.22% reduction of power as compared to semi custom design.
  • 关键词:ADDER; MICROWIND; TRANSMISSION GATE; VLSI
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