期刊名称：International Journal of Computer Trends and Technology
电子版ISSN：2231-2803
出版年度：2011
卷号：2
期号：1
出版社：Seventh Sense Research Group
摘要：Test power is major issue of recent scenario of VLSI testing. There are many test pattern generation techniques for testing of combinational circuits with different tradeoffs. The don’t care bit filling method can be used for effective test data compression as well as reduction in scan power. This paper gives a new advancement in automatic test pattern generation method by feeling don’t care bit of the test vector to optimize the switching activities. Finally this concept produces low power testing.
关键词：ATPG test vector generation; Huffman code; Parity bit generation; Switching activity
