We revisit the gate elimination method, generalize it to prove correlation bounds of boolean circuits with Parity, and also derive deterministic #SAT algorithms for small linear-size circuits. In particular, we prove that, for boolean circuits of size 3 n − n 0 51 , the correlation with Parity is at most 2 − n (1) , and there is a #SAT algorithm running in time 2 n − n (1) ; for circuit size 2 99 n , the correlation with Parity is at most 2 − ( n ) , and there is a #SAT algorithm running in time 2 n − ( n ) . Similar correlation bounds and algorithms are also proved for circuits of size almost 2 5 n over the full binary basis B 2 .