出版社：Electronics and Telecommunications Research Institute
摘要：This paper presents a delay-locked-loop-based clock and data recovery (CDR) circuit design with a nB(n+2)B data formatting scheme for a high-speed serial display interface. The nB(n+2)B data is formatted by inserting a '01' clock information pattern in every piece of N-bit data. The proposed CDR recovers clock and data in 1:10 demultiplexed form without an external reference clock. To validate the feasibility of the scheme, a 1.7-Gbps CDR based on the proposed scheme is designed, simulated, and fabricated. Input data patterns were formatted as 10B12B for a high-performance display interface. The proposed CDR consumes approximately 8 mA under a 3.3-V power supply using a 0.35- CMOS process and the measured peak-to-peak jitter of the recovered clock is 44 ps.
关键词：Clock data recovery (CDR);delay-locked loop (DLL);nB(n+2)B data formatting scheme;high-speed serial interface;display interface
