出版社：Electronics and Telecommunications Research Institute
摘要：In this paper, the design of a low-power 512-bit synchronous EEPROM for a passive UHF RFID tag chip is presented. We apply low-power schemes, such as dual power supply voltage (VDD=1.5 V and VDDP=2.5 V), clocked inverter sensing, voltage-up converter, I/O interface, and Dickson charge pump using Schottky diode. An EEPROM is fabricated with the 0.25 EEPROM process. Power dissipation is 32.78 in the read cycle and 78.05 in the write cycle. The layout size is 449.3 480.67 .
