期刊名称：International Journal of Computer Science and Information Technologies
电子版ISSN：0975-9646
出版年度：2014
卷号：5
期号：2
页码：2033-2037
出版社：TechScience Publications
摘要：This paper demonstrates an asynchronous implementation of a FIFO based on 4 phase bundled data protocol, interfaced with an SRAM. Both FIFO and SRAM are modeled using VHDL and use the asynchronous handshaking principles for communication. Timing and power analysis for the design is also presented. The synthesis, simulation and analysis is done with the help of Xilinx ISE version 9.1i
关键词：asynchronous; FIFO; SRAM; interfacing; VHDL;delays; power
