期刊名称：International Journal of Computer Science and Information Technologies
电子版ISSN：0975-9646
出版年度：2014
卷号：5
期号：3
页码：4015-4018
出版社：TechScience Publications
摘要：This paper demonstrates the reversible logic synthesis for the n-to-2n decoder, where n is the fault tolerant Fredkin and Feynman double gates. Thus, the entire scheme inherently becomes fault tolerant. Algorithm for designing the generalized decoder has been presented. In addition, several lower bounds on the number of constant inputs, garbage outputs and quantum cost of the reversible fault tolerant decoder have been proposed.Transistor simulation of the proposed design are shown in microwind 3.0 version where power area and delay are calculated
