期刊名称：International Journal of Computer Science and Information Technologies
电子版ISSN：0975-9646
出版年度：2014
卷号：5
期号：3
页码：4124-4127
出版社：TechScience Publications
摘要：In digital systems, the filters occupy a major role. This paper reviews several techniques used for designing & implementing low power area efficient digital filters & it presents the methods to reduce dynamic power consumption of a digital Finite Impulse Response (FIR) filter. This work describes the design of parallel FIR filter structures using polyphase decomposition technique, that requires minimum number of multipliers and low power adders. Normally multipliers consume more power and large area than the adders. For reducing the area, this filter structure uses adders instead of multipliers since the adder requires low power and less area than the multipliers. Moreover, number of adders does not increase along with the length of parallel FIR filter. This paper reviews those techniques, which saves the multipliers, for example for a 3 parallel 27 tap FIR filter saves 8 multiplier and 3 parallel 147 tap FIR filter saves 48 multipliers. The FIR filter was synthesized implemented using Xilinx ISE V10.1 and Virtex IV FPGA to target device xc3s250e
关键词：Fast Finite-impulse response (FIR) algorithms;(FFAs); Digital Signal Processing(DSP); Parallel FIR
