期刊名称：International Journal of Computer Science and Information Technologies
电子版ISSN：0975-9646
出版年度：2015
卷号：6
期号：3
页码：3198-3201
出版社：TechScience Publications
摘要：In this paper a new area efficient, high-speed and ultra-low power 1-bit full adder cell is presented. The performance: power, time delay and power delay product (PDP) of the proposed adder cell has been analyzed in comparison with the four existent low-power, high-speed adders. The circuits being studied are optimized for energy efficiency at 0.18-μm CMOS process technology and intensive simulation runs on Cadence environment shows that the new full adder has more than 16% in power savings over C-CMOS full adder.
