期刊名称：International Journal of Computer Science and Information Technologies
电子版ISSN：0975-9646
出版年度：2015
卷号：6
期号：5
页码：4206-4211
出版社：TechScience Publications
摘要：Bit-sequential multiplier is being studied in a (+1, -1) binary representation. The maximum length of multiplier for a fix point numbers consists of n module. Each module is a five bit adder which contains 5 inputs and 3 outputs. It also contains an additional pin at the input as well as at the output. Computation time for multiplication is of the order of O(n). Hardware realization of module is being discussed. In this design the input generated bit sequentially and the output is also generated bit sequentially. The model is being compared with the bit sequential multiplier in conventional binary system and the merits and demerits are described in detail.
关键词：Add-shift multiplier; (+1; -1);Representation; Carry-save addition; unified way
