期刊名称：International Journal of Soft Computing & Engineering
电子版ISSN：2231-2307
出版年度：2014
卷号：4
期号：2
页码：18-23
出版社：International Journal of Soft Computing & Engineering
摘要：Floating point multiplier is one of the vital concerns in every digital system. In this paper, the concepts of High speed compressors are used for the implementation of a High speed single precision binary Floating point multiplier by using IEEE 754 standard. Since compressors are special kind of adder which is capable to add more number of bits at a time, the use of these compressors makes the multiplier faster as compared to the conventional multiplier. For Mantissa calculation, a 24×24 bit multiplier has been developed by using these compressors. Owing to these high speed compressors, the proposed multiplier obtains a maximum frequency of 1467.136MHz. It is implemented using Verilog HDL and it is targeted for Xilinx Virtex-5 FPGA.
关键词：Compressors; Floating point multiplier; Mantissa; IEEE754 standard; Verilog HDL
